Method for generating i/q signal in a tdma transmitter and corresponding modulator

ABSTRACT

The present invention relates to a digital I/Q modulator which efficiently supports multi-time-slot operation of wireless (TDMA transmitters employing linear power amplifiers. According to the present invention, dips are introduced in the envelope of the I/Q signal in the guard interval between adjacent time-slots or bursts. The dips avoid interference on adjacent radio frequency channels when the gain of the TX chain in switched abruptly in order to change the power level of the TX signal or when the modulation scheme is changed. Also, a method is provided for generating the dips, which is particularly attractive if the modulation scheme in adjacent time-slots changes from GMSK to 8PSK or vice versa.

The present invention relates to a modulator for generating a digitalI/Q signal having a plurality of time-slots, to a signal processingmethod for generating a digital VQ signal having a plurality oftime-slots and to a computer program for a time division multiple access(TDMA) transmitter for a global system for mobile communications (GSM),enhanced data rates for GSM evolution (EDGE) or enhanced general packetradio service (EGPRS) system.

In 1997, a suggestion for EDGE was filed at the European StandardizationInstitute, ETSI. The standardization of EDGE will be carried out in twophases. A part of the first phase specifies EGPRS, which is an extensionof the existing GPRS. EGPRS introduces the 8PSK (phase shift keying)modulation scheme, which has the potential for higher data rate than theestablished GMSK (Gaussian minimum shift keying) modulation scheme. Thisnew 8PSK modulation scheme has more stringent requirements with respectto the linearity of the power amplifier in the TX (transmission) chainsince, in contrast to GMSK, the amplitude is not constant. Therefore,while the constant envelope of the GMSK enabled the employment of asaturated power amplifier (PA), which is more power efficient than alinear PA, the variable envelope of the 8PSK modulation scheme demandsfor a linear PA.

When the 8PSK modulation scheme is employed in multi-time slot (TS)operation. It is required to adjust the TX power for every TSindividually as demanded by the BSC. The TX power transient between theTSs should be smooth. Otherwise, if the TX power transient between theTSs is not smooth, interferences may occur with other users on adjacentchannels. Due to this, it is normally not possible to simply switch thegain of the TX path abruptly. In addition to that, the gain of the TXpath is usually varied in the analogue domain. Due to this, a continuousvariable gain amplifier (VGA) is required in the TX chain, for adjustingthe TX power level. Such a VGA is controlled by an appropriately shapedanalogue control voltage. The provision of a VGA and the generation ofthe appropriately shaped analogue control voltage are expensive. Inaddition to that, such an arrangement is prone to defects, which areinherent to such an analogue circuitry. In addition to that, such ananalogue circuitry has tolerances which, as known to the person skilledin the art, are always trouble to deal with.

Another problem arises in multi TS operation, when the modulation schemein adjacent TSs is changed from 8PSK to GMSK or vice versa: such aswitching between 8PSK and GMSK may provoke discontinuities in thedigital I/Q signals. Such discontinuities must be avoided since they arevery broadband and may cause interference on other channels.

The requirement for smooth TX power ramping is fundamental to anymultiple access system, which combines TDMA and frequency divisionmultiple access (FDMA). Therefore, the applied standards reserve a timeinterval between adjacent TSs, which is dedicated to power ramping andin which no data transfer occurs.

According to the GSM standard, this time interval is denoted as “guardinterval”.

The introduction of GPRS led to the extension of the first methodtowards multi time slot operation. Here, the power ramping voltage has astep shape with smooth edges.

It is an object of the present invention to minimize interferencesbetween adjacent time slots.

According to an exemplary embodiment of the present invention, thisobject is solved with a modulator for generating a digital I/Q signalhaving a plurality of time slots, the modulator comprising means forintroducing a dip in an envelope of the digital I/Q signal in a guardinterval between adjacent time slots of the plurality of time slots.

Such modulator according to an exemplary embodiment of the presentinvention as set forth in claim 1 allows the use of a linear poweramplifier in the digital I/Q modulator supporting multi time slotoperation of wireless TDMA transmitters. In other words, thedifficulties, which are encountered in a linear transmitter for EGPRS,may be overcome by introducing dips in the envelope of the digital orI/Q signal during the guard interval between adjacent time slots.Furthermore, the introduction of dips in the envelope of the digital orI/Q signal may have the effect that unwanted abrupt switching transientsin the TX signal due to abrupt switching of the gain of the TX path canbe avoided. This can be done by switching the gain of the TX path duringthe dip in the I/Q signal when the TX signal is down. Accordingly,interference between adjacent channels occurring with a change of the TXpower level between adjacent time slots is minimized.

Furthermore, with the introduction of dips in the envelope of thedigital I/Q signal during the guard interval between adjacent timeslots, unwanted discontinuities in the I/Q signal when switching betweenthe 8PSK and the GMSK modulation scheme may be avoided. Accordingly,interferences in adjacent channels occurring when switching between 8PSKand GMSK may be minimized.

Furthermore, a discrete gain VGA rather than a continuous gain VGA maybe employed in the modulator. Also, since the dips are introduced in thedigital domain, there is no trouble with tolerances of analoguecircuitry. In addition to that, the present invention makes a generationof the analogue control voltage for the continuous VGA obsolete.

According to another exemplary embodiment of the present invention asset forth in claim 2, both, the I and the Q signal are multiplied with adip-shaped waveform which allows for a very simple solution forintroducing the dips.

According to an exemplary embodiment of the present invention as setforth in claim 3, the dip shaping is for free because the pulse shapingfilter is usually provided for 8PSK.

According to an exemplary embodiment of the present invention as setforth in claim 4, zeros are filled into the pulse shaping filter duringthe guard interval. By filling zeros into the pulse-shaping filterduring the guard interval, the dip is introduced in the envelope of thedigital I/Q signal. Since the generation of digital zeros is simple andnot prone to malfunctions, a very simple and stable modulator avoidinginterference between adjacent channels is provided.

Yet another exemplary embodiment of the present invention, as set forthin claim 5, allows for the efficient introduction of the dips into theenvelope when GMSK modulated time-slots are involved. Furthermore, theexemplary embodiment of the present invention as set forth in claim 5,allows for a re-use of a C0 filter for the GMSK instead of anindependent GMSK modulator.

According to another exemplary embodiment of the present invention, asset forth in claim 6, the modulator is a GMSK modulator and a 8PSKmodulator and allows to use both modulations schemes, the GMSKmodulation scheme and the 8PSK modulation scheme.

According to yet another exemplary embodiment of the present inventionas set forth in claim 7, a signal processing method is provided, whichminimizes interference in adjacent channels.

According to yet other exemplary embodiments of the present invention asset forth in claims 8 and 9, signal processing methods are provided,wherein the dips are generated by a multiplication of the I signal andthe Q signal with dip-shaped waveforms and by means of the pulse shapingfilter. Both methods allow a very simple and efficient control of themodulation. Also, if the dip is introduced by means of the pulse shapingfilter, the dip shaping is for free.

According to the present invention, there is also provided a computerprogram for a TDMA transmitter for a GSM-, EDGE- or EGPRS-system as setforth in claim 10.

As apparent from the above, a digital I/Q modulator is suggested whichefficiently supports multi-time slot operation of wireless TDMAtransmitters employing a linear power amplifier. It is an aspect of thepresent invention to introduce dips in the envelope of the digital I/Qsignal in the guard interval between adjacent time slots. These dipsavoid interference on adjacent radio frequency channels when the gain ofthe TX chain is switched abruptly, in order to change the power of theTX signal. In addition, a signal processing topology is suggested forgenerating the dips which is in particular attractive if the modulationscheme in adjacent time slots changes from GMSK to 8 PSK, or vice versa.

These and other aspects of the present invention will be apparent fromand elucidated with reference to the embodiments described hereinafter.These embodiments will be described with reference to the followingFigures:

FIG. 1 shows a single slot 8PSK I/Q modulator according to an aspect ofthe present invention.

FIG. 2 shows a setting of the 8PSK MUX of the modulator of FIG. 1 duringbegin and at the end of a burst according to an aspect of the presentinvention.

FIG. 3 shows a single slot quadratic GMSK I/Q modulator according to anaspect of the present invention.

FIG. 4 shows a setting of the GMSK multiplexer in the modulator of FIG.3 during begin and end of a time slot according to an aspect of thepresent invention.

FIG. 5 shows a modulator with a digital multiplier for multiplying thedigital I/Q signals with a dip-shaped waveform according to an aspect ofthe present invention.

FIG. 6 shows a multi-slot 8PSK/GMSK I/Q modulator, according to anaspect of the present invention.

FIG. 7 shows a Finite State Machine (FSM) in the quadratic branch of theGMSK modulator of FIG. 6, according to an aspect of the presentinvention.

FIG. 8 shows a setting of the C0 MUX and the C1 MUX of the modulator ofFIG. 6 during the transition between an 8PSK time slot and a GMSK timeslot, and vice versa, according to an aspect of the present invention.

FIG. 9 illustrates by means of a hypothetical multi-slot TX envelope aswitching between 8PSK and GMSK at different power levels in adjacenttime slots.

In the following description of the above Figures, the same referencenumbers are used for the same or corresponding elements.

FIG. 1 shows a simplified circuit diagram of a single slot 8PSK I/Qmodulator 1, according to an aspect of the present invention. When themodulator of FIG. 1 is applied in a GSM system, the speech signal isquantized in the speech coding, and then, the quantized speech signal isorganized into data frames during channel coding. The serial data streamis then introduced into the serial to parallel converter 2, which maybe, as shown in FIG. 1, a three-bit serial to parallel converter. Thethree-bit parallel signal is then input to a Grey Mapper 3 which mapseach bit triplet on one out of eight complex signals. Then, a 3π/8rotation is carried for each symbol by means of complex multiplier 4.This is done to avoid zero crossings in the RF envelope. After amultiplexing of the signal in the multiplexer (MUX) 5, the output of theMUX 5 is input to an up-sampler 6 by which carries out an up-samplingN=16, which inserts N-1 zeros after every input sample. The output ofthe up-sampler 6 is input to a Finite Impulse Response (FIR)pulse-shaping filter, here referred to with CO. In another exemplaryembodiment, up sampling and FIR filtering may be merged in a moreefficient polyphase interpolation filter structure. The output of theFIR 7 is input to a digital to analogue converter (DAC)8.

During operation, the MUX 5 selects between zeros during the guardperiod of the TDMA signal, and rotated 8PSK symbols during the activepart of the burst. This is illustrated in further detail in FIG. 2.

FIG. 2 shows a setting of the 8PSK MUX 5 of FIG. 1 during begin and endof a burst. As can be taken from FIG. 2, during the guard symbols, zerosare filled into the MUX 5. During the leading three tail symbols, thedata symbols and the trailing three tail symbols, the rotated 8PSKsymbols are inserted into the MUX 5. At the end of the data symbol, the8PSK symbol is maintained at the MUX 5 until the end of the three tailsymbols. With the beginning of the following guard symbols, zeros areinserted into the MUX 5.

Feeding the up-sampler/filter with zeros has the following effect: theleading zeros enable a smooth step-on response of the filter when it isexcited by the early rotated 8PSK symbols. The trailing zeros fillingthe late rotated 8 PSK symbols enable a smooth step-off response.

FIG. 3 shows an exemplary embodiment of a single slot quadratic GMSK I/Qmodulator 9, according to an aspect of the present invention. FIG. 3 isa simplified circuit diagram. GMSK is a non-linear modulation schemewith pulse-shaping in the phase domain in contrast to linear modulationschemes with pulse shaping in the I/Q domain. As suggested in P. Jung's,“Laurent's decomposition of Binary Digital Continuous Phase ModulatedSignals with Modulation Index 1/2 Revisited” IEEE transactions oncommunications, vol. 42, No. 2/3/4, 1994, one may implement a GMSKmodulator by superimposing a series of linearly modulated signals. Thecorresponding shaping filters are denoted as C0, C1, . . . Cn.

The input of the FIR filter C0 14 is generated as follows: the GMSK bitsare inserted into a mapper 10. The output signal of the mapper 10 isinput to a digital multiplier 11, which multiplies the output signals ofthe mapper 10 with a complex phasor e^(jkπ/2). The multiplied signalsare provided to a MUX 12 which output signals are provided to anup-sampler 13, corresponding to the up-sampler 6 in FIG. 1. The outputsignal of the up-sampler 13 is input to the FIR filter C0 14 whichoutput signal is added to the output signal of FIR filter C1 21 andsupplied to the DAC 15. The DAC 15 corresponds to the DAC 8 of FIG. 1.

The input of the FIR filter C1 21 is obtained from the modulating bitsby applying a Finite State Machine (FSM) 16, a mapper 17 and amultiplication by means of a digital multiplier 18 with a complex phasore^(j(k−1)π/2). The output signal of the digital multiplier 18 is inputinto the MUX 19 which output signal is provided to the up-sampler 20.The output signal of the up-sampler 20 is provided to the FIR filter C121. The up-sampler 20 corresponds to the up-sampler 6 of FIG. 1.

In general, the input of a shaping filter Cn is obtained from themodulating bits by applying a FSM, a mapper and a multiplication with acomplex phasor e^(jkπ/2). The FSM algorithm and the phase θ_(n) of thephasor depend on the index n of the element of the series. Accordingly,as shown in FIG. 3, for n=0, no FSM at all is required and θ₀=0 applies.Since merely the 0^(th) element of the series is used, this is denotedas linearized GMSK. Accordingly, the upper branch in FIG. 3 is referredto as linear branch of the GMSK modulator. Here, it is to be noted thatthe C0 filter is adopted as the shaping filter for 8PSK to obtain apower spectral density (PSD) which is similar to the PSD of the GMSK. Byconsidering the higher order elements of the series, the approximationerror can be made arbitrarily small. In the practical application, it issufficient to consider just the elements 0 and 1 of the series. Thelower branch of the modulator of FIG. 3 is also referred to as quadraticbranch of the GMSK modulator.

The quadratic GMSK modulator as shown in FIG. 3 has the advantage thatthe pulse-shaping filters may be applied for envelope shaping in thesame way as described with reference to the 8PSK modulator depicted inFIG. 1. This will be described further with reference to FIG. 4.

FIG. 4 shows an exemplary setting of the MUXs 12 and 19 of FIG. 3 duringbegin and an end of a time slot or burst. The left-hand side of FIG. 4shows the setting during begin of a time slot and the right-hand side ofFIG. 4 shows the setting at the end of a time slot. As may be taken fromFIG. 4, zeros are inserted by the MUXs 12 and 19 during all guard bitsexcept the last guard bit of the leading guard interval and the firstguard bit of the trailing guard interval. From the last bit of theleading guard interval to the first bit of the trailing guard interval,the GMSK signals are supplied to the u-samplers 13 and 20. This settingof the innermost and outmost guard symbols to the GMSK signals iscompulsory for GMSK, because the phase error in the region of theoutermost tail bits would otherwise increase too much.

The modulator of FIG. 3 with a setting of MUXs 12 and 19 as shown inFIG. 4 allows for smooth edges of the TX envelope.

FIG. 5 shows a simplified sketch of a digital I/Q modulator 22,comprising digital multipliers 23. I/Q signals are provided to thedigital multipliers 23 which multiply each I signal and each Q signalwith a dip-shaped waveform generating digital signals I′ Q′ having a dipin the envelope. The digital multipliers 23 introduce the dips in theenvelope of the digital VQ signal in the guard interval of subsequenttime slots. In principle, the digital I/Q modulator may be a 8PSKmodulator 1, as shown in FIG. 1, a GMSK modulator 9, as shown in FIG. 3,or a combination of both modulators 1 and 9, or parts thereof.

FIG. 6 shows a multislot 8PSK/GMSK I/Q modulator 24, according to anexemplary embodiment of the present invention. On a first glance, themodulator 24 of FIG. 6 is a combination of the 8PSK modulator 1 of FIG.1 and the quadratic GMSK modulator 9 of FIG. 3. The modulator 24 of FIG.6 comprises an 8PSK modulator comprising the three-bit serial toparallel converter 2, the grey mapper 3, the complex multiplier 4, amultiplexer 26 referred to as C0 MUX which will be described in thefollowing, an up-sampler 6 and a FIR filter C0 7. A linear branch of theGMSK modulator comprises the mapper 10, the complex multiplier 11, theC0 MUX 26, the up-sampler 6 corresponding to the up-sampler 13 of FIG. 3and the FIR filter C0 7 corresponding to the FIR filter C0 14 of FIG. 1.A quadric branch of the GMSK modulator, comprises the FSM 16, the mapper17, the complex multiplier 18, the GMSK MUX 19, now referred to as C1MUX, the up-sampler 20 and FIR filter C1 21. Furthermore, the modulator24 of FIG. 6 has a multiplexer 25 which provides the serial data streamto be modulated with the 8PSK modulation scheme to the serial toparallel converter 2, and which provides the serial data stream to bemodulated with the GMSK modulation scheme to the mapper 10 and the FSM16. In case the 8PSK modulation scheme is applied, the output signal ofthe FIR filter C0 is provided directly to the DAC 8. In case the GMSKmodulation scheme is applied, the output of the FIR filter C0 7 and ofthe FIR filter C1 21 are added and applied to the DAC 8. Themultiplexers C0 MUX 26, C1 MUX 19 and multiplexer 25 enable the two-modeoperation of the modulator: the 8PSK mode and the GMSK mode.Furthermore, these multiplexers enable configuration of the modulator as8PSK modulator, GMSK modulator or linearized GMSK modulator.

FIG. 7 shows the Finite State Machine 16 and the quadratic branch of theGMSK modulator with more detail. As can be taken from FIG. 7, the FSM 16comprises a first register 30 and a second register 31 and a firstmodulo 2 adder 32 and a second modulo 2 adder 33. The input of the FSM16 is provided to the first register 30 and to the modulo 2 adder 32.The output of the first register 30 is provided to the second register31 and to the first modulo 2 adder. The outputs of the second registers31 and the first modulo 2 adder 32 are provided to the second modulo 2adder 33 and then output to the mapper 17.

A sequence of the C0 MUX 26 and C1 MUX 19 settings during the transitionfrom an 8PSK burst to a GMSK burst is depicted in FIG. 8.

FIG. 8 shows an exemplary setting of C0 MUX 26 and C1 MUX 19 during thetransition from an 8 PSK time slot and a GMSK time slot and vice versaAs may be taken from FIG. 8, the C0 MUX 26 provides in the 8PSK mode the8PSK signal to the up-sampler 6 throughout the data signal and the threetail symbols. Then, during the first seven guard symbols, the C0 MUX 26provides zeros to the up-sampler 6. During the last guard symbol, the C0MUX 26 provides the GMSK signal of the linear branch of the GMSKmodulator to the up-sampler 6. Then, during the three tail symbols andthe following data symbols, the C0 MUX 26 provides the GMSK signal ofthe linear branch of the GMSK modulator, i.e. the signal output by thecomplex multiplier 11 to the up-sampler 6.

The C1 MUX 19 provides zeros to the up-sampler 20 during the datasymbol, where the 8 PSK signal is provided to the DAC 8, during thethree tail symbols, while the 8PSK signal is provided to the DAC 8during the first seven bits of the eight guard symbols. Then, when thesignal is switched to the GMSK signal, the C1 MUX 19 provides the GMSKsignal of the quadratic branch of the GMSK modulator, i.e. the output ofthe complex multiplier 18 to the up-sampler 20 during the last, i.e. theeighth bit of the eight guard symbols of the guard interval. Then,during the three tail symbols and the data symbols, the output of thecomplex multiplier 18 is provided to the up-sampler 20.

In case it is switched from a time slot to which the GMSK modulationscheme is applied to a subsequent time slot applying the 8PSK modulationscheme, the C0 MUX 26 provides the output signal of the complexmultiplier 11 to the up-sampler 6 during the data symbols, during thethree tails symbols and during the first symbol of the eight guardsymbols. Then, the C0 MUX 26 provides seven zeros during the remainingseven guard symbols to the up-sampler 6. With the start of thesubsequent three tail symbols of the subsequent time-slot with the 8PSKmodulation scheme, the C0 MUX 26 provides the output signal of thecomplex multiplier 4 to the up-sampler 6 during the tail symbols and thedata symbols.

When a switching from the GMSK modulation scheme to the 8PSK modulationscheme is performed for subsequent time slots, the C1 MUX 19 providesthe output signal of the complex multiplier 18 to the up-sampler 20during the data symbols during the three tail symbols and during thefirst one of the eight guard symbols. Then, for the remaining seven bitsof the guard symbol, for the following tail symbol and following datasymbol where the 8PSK is performed, the C1 MUX 19 provides zeros to theup-sampler 20.

FIG. 9 shows an example of a hypothetical multi-slot TX envelope pt andthe corresponding power p_(n) which can be observed in an adjacentchannel when a switching is performed from 8PSK in one slot to GMSK inthe following slot The average power in the 8PSK TS is assumed higherthan the average power in the GMSK TS. As may be taken from FIG. 9, inthe envelope p_(tx) between the 8PSk modulation scheme in the first slotand the GMSK modulation scheme in the second slot there is, according toan exemplary embodiment of the present invention, a dip. This dip isinserted, as explained in detail above, by either multiplying both I andQ signals with the dip-shaped waveform or by provoking a step-offresponse followed by a step-on response of the pulse-shaping filter, byfilling the pulse-shaping filters with zeros. In spite of the fact thatFIG. 9 shows a relatively small dip, the size of the dip may be varied,in accordance with the requirements in the respective system. As shownby the adjacent channel power p_(n), the smooth dip in the TX enveloperesults in a transition in the adjacent channel power without showing adistinct peak. The dip is not resolved because it lasts shorter than thetime constant of the resolution filter. Accordingly, the effect of thedip is to avoid steps in the I/Q signal due to switching the modulationscheme and to hide steps in the TX envelope due to switching of thepower levels in subsequent time slots. As shown in FIG. 9, theintroduction of the dip in the envelope allows to minimize interferencein adjacent channels.

As already explained in detail above, the two multiplexers C0 MUX 26 andC1 MUX 19 serve for feeding complex value zeros rather than the complexvalue symbols into the up-samplers 6 and 20 which proceed thepulse-shaping filters FIR C0 7 and FIR C1 21. As already indicatedabove, it is also possible to further consider higher order branchesother than the 0 and the 1 branch to improve the approximation in themodulator 24, as depicted in FIG. 6. Also, as a variant, it may bepossible to combine the respective up-sampler with the subsequentpulse-shaping FIR filters into an efficient polyphase interpolationfilter.

Advantageously, the modulator 24 as shown in FIG. 6 allows the use of alinear power amplifier, while avoiding interferences between adjacentchannels. Also, a simple discrete gain VGA may be employed rather than acontinuous gain VGA. Since the signal processing according to thepresent invention is carried out in the digital domain, no problems withtolerances of analogue circuits are encountered. Also, a generation ofan analogue control voltage for a continuous VGA is made obsolete.

Due to the employment of the multiplexers C MUX 26 and C MUX 19 in themodulator 24 of FIG. 6, the dip-shaping is for free, since the filtersand upsamplers are required anyway. Also the modulator 24 allows asimple control of the modulation and the double use of the FIR filter C07 for the linear branch of the GMSK modulator and the 8PSK modulator. Amodulator such as modulator 24 may preferably be used, for example, inGSM-, EDGE- or in EGPRS chipsets.

According to another exemplary embodiment of the present invention,advantageously, the retarding timing elements of the FIR filters, whichare filled during regular operation sequentially, may be filled alsowith preferably initial values in parallel. This allows for additionalfreedom in the design of the transitions between time slots. Thus, forexample, during the application of particular transmission concepts, itmay be preferable to abruptly insert a GMSK modulated signal having aconstant envelope at the beginning of the guard period after the smoothdown ramping of a 8 PSK time slot. According to an exemplary aspect ofthe present invention, advantageously, this may also be achieved by aparallel loading of suitable initial values.

1. Modulator for generating a digital I/Q signal having a plurality oftime-slots, the modulator comprising means for introducing a dip in anenvelope of the digital I/Q signal in a guard interval between adjacenttime-slots of the plurality of time-slots.
 2. Modulator according toclaim 1, wherein the means for introducing the dip in the envelope ofthe digital I/Q signal in the guard interval between adjacent time-slotsof the plurality of time-slots comprises a digital multiplier formultiplying the I signal and the Q signal of the I/Q signal with adip-shaped waveform.
 3. Modulator according to claim 1, furthercomprising apulse shaping filter and wherein the means for introducingthe dip in the envelope of the digital I/Q signal in the guard intervalbetween adjacent time-slots comprises means for generating a step-offresponse followed by a step-on response of the pulse shaping filter suchthat the dip is introduced in the envelope of the digital I/Q signal inthe guard interval between adjacent time-slots.
 4. Modulator accordingto claim 3, wherein the means for generating the step-off responsefollowed by the step-on response of the pulse shaping filter comprisesmeans for filling digital zeros into the pulse shaping filter during theguard interval such that the dip is introduced in the envelope of thedigital I/Q signal in the guard interval between adjacent time-slots. 5.Modulator according to claim 3, further comprising a GMSK modulator witha linear branch and a quadratic branch and a multiplexer, wherein themultiplexer feeds complex zeros into the branches such that the step-offresponse is followed by a step-on response of the pulse shaping filtersuch that the dip is introduced in the envelope of the digital I/Qsignal in the guard interval between adjacent time-slots.
 6. Modulatorin accordance with claim 1, wherein the modulator is a GMSK modulatorand a 8PSK modulator.
 7. Signal processing method for generating adigital I/Q signal having a plurality of time-slots, the signalprocessing method comprising the steps of: (a) modulating the I signaland the Q signal for generating the I/Q signal; and (b) introducing adip in an envelope of the digital I/Q signal in a guard interval betweenadjacent time-slots of the plurality of time-slots.
 8. Signal processingmethod according to claim 7, further comprising the step of multiplyingthe I signal and the Q signal of the I/Q signal with a dip-shapedwaveform.
 9. Signal processing method according to claim 7, wherein step(b) of introducing the dip in the envelope of the digital I/Q signal inthe guard interval between adjacent time-slots further comprises thestep of: generating a step-off response followed by a step-on responseof the pulse shaping filter such that the dip is introduced in theenvelope of the digital I/Q signal in the guard interval betweenadjacent time-slots.
 10. Computer program for generating a digital I/Qsignal having a plurality of time-slots, in particular for a chipset forimplementing a TDMA transmitter in a GSM-, EDGE- or EGPRS-system, thecomputer program comprising the steps of: (a) modulating the I signaland the Q signal for generating the I/Q signal; and (b) introducing adip in an envelope of the digital I/Q signal in a guard interval betweenadjacent time-slots of the plurality of time-slots.
 11. Transmittercomprising a modulator according to claim 1.